1. Field of the Invention
The present invention generally relates to circuit timing analysis and more particularly to an improved circuit timing analysis that reduces delay pessimism by using multiple switching windows.
2. Description of the Related Art
During the design phase of electronic signal processing equipment, such as integrated circuit chips, the timing at which different signals pass through various portions of the device must be studied to ensure that the device operates as planned. For example, it is important to analyze the design of the device so as to make sure the flow of signals reach their destination at the proper time. This is necessary to maintain the proper logical operations of the electronic device. In addition, the circuit designer needs to account for (and if possible to avoid) situations where concurrent signal transitions occur on closely spaced electrical wires, because such a situation could delay the transmission of the signals along their respective wires as a result of the unavoidable capacitive coupling between such closely spaced wires.
As the number of logical devices within each integrated circuit chip increases, the number of signal paths which may lead to a specific logical device (“fan-in”) and the number of signal paths to which a specific logic of device may pass a signal (“fan-out”) increases exponentially. In order to maintain the timing of the various signals within the boundaries prescribed by the circuit designer and to identify situations in which concurrent signal transitions occur on closely spaced wires, conventional timing analysis systems create a logical “window” in which a signal can be expected to arrive at a given logical device given the fan-in to that device. This window increases as the size and complexity of the fan-in leading to the logical device increases.
Conventional static timing analysis operates on a timing graph representing an abstraction of the logic network within an integrated circuit. The abstraction consists of nodes at which arrival times (ATs), required arrival times (RATs), and/or slews are computed, and directed delay edges on which delays connecting these nodes are computed. Normally both early mode and late mode values are computed, and test edges may be present in the delay graph representing ordering requirements between the early and late mode ATs on the pair of nodes connected by the test edge.
The times (ATs and RATs) computed by static timing analysis are normally made with respect to some specific time within a repeating clock cycle. The early mode AT represents the earliest that the signal at the node can change from the stable value which it held during the previous clock cycle and its value at a node is computed as the minimum over all incoming delay edges of the early mode AT at the source of the delay edge plus the early mode delay associated with that delay edge. The late mode AT represents the latest that the signal at the node can take on its final stable value during the current clock cycle and its value at a node is computed as the maximum over all incoming delay edges of the late mode AT at the source of the delay edge plus the late mode delay associated with that delay edge. Thus the “window” from the early mode AT to the late mode AT represents the period during which the signal at the node may be switching. Note that if many paths converge on the node, the signal at the node may switch many times during this window, it may switch only once, or not at all.
In analysis of the effects of signal coupling on delay and noise and in the analysis of peak current demand for power bus analysis, it is important to understand the times during which a signal can switch. To determine the effects of coupling on delay of a first wire, one must determine whether a neighboring wire is switching at the same time as a transition of interest is occurring in the first wire. To determine whether coupling to a first wire of the effects of a transition on an adjacent wire could cause an erroneous data to be imposed on the first wire and thus cause the circuit to produce incorrect results, it is important to understand the periods during which the results of erroneous values on the first wire could be saved into memory elements, and then to determine whether or not the adjacent wire may be switching during these periods. The time of occurrence of a transition of interest on a first wire for delay analysis, or the period during which noise coupled onto a first wire could cause erroneous results to be latched into some memory element for noise analysis, are referred to as the victim windows of the first wire for the respective analyses. In determining peak current demand, one must determine all of the signals within a region of interest which could be switching at a particular time, and must therefore determine the possible switching windows for each signal. The smaller these switching windows can be made, the less pessimistic are these analyses. However, conventional analysis only provides a single window for the static timing analysis. This requires that the window be unnecessarily large (e.g., overly pessimistic) to accommodate all possible timing situations. The invention discussed in detail below reduces the size of the window by using multiple windows. Therefore, the invention is less pessimistic than conventional systems because the smaller windows used with the invention result in a smaller number of possible simultaneous switching situations, thereby allowing more circuit designs to be found acceptable than the conventional systems that are more pessimistic and would reject more circuit designs. In the following description, the arrival, existence, or presence of a signal on a wire or net at a particular time or within a particular time window will be understood to mean the occurrence of a transition on that wire or net at that time or during that time window.